1. Field of the Invention
The present invention relates to a solid-state image pickup element, a method of manufacturing the same, and an image pickup apparatus including the same.
2. Description of the Related Art
It is known that in a CCD solid-state image pickup element and a CMOS solid-state image pickup element, crystal defects in a photodiode, and interface states in an interface between a light receiving portion formed on a silicon substrate, and an insulating layer formed on the light receiving portion cause a dark current.
FIG. 13A is a schematic cross sectional view explaining the case where an insulating layer is formed on a silicon layer having a photodiode formed therein. FIG. 13B is an energy diagram of the structure shown in FIG. 13A. As shown in FIGS. 13A and 13B, interface states each indicated by a mark x occur in an interface between a silicon layer 51 having a photodiode PD formed therein, and an insulating layer 52 formed on the silicon layer 51. These interface states become a generation source of a dark current, and electrons originating in the interface are caused to flow in the form of the dark current into the photodiode PD.
In order to cope with this situation, a so-called Hole Accumulation Diode (HAD) structure is adopted as a technique for controlling the generation of the dark current. This technique, for example, is described in Japanese Patent Laid-Open No. 2005-123280 (referred to as Patent Document 1 hereinafter).
FIG. 14A is a schematic cross sectional view explaining the case where an HAD structure is obtained by forming a p+-type semiconductor region. FIG. 14B is an energy diagram of the HAD structure shown in FIG. 13A. Specifically, as shown in FIGS. 14A and 14B, a p-type impurity is introduced into the neighborhood of a surface of a silicon layer 51 to form a p+-type semiconductor region, and the resulting p+-type semiconductor region is made a positive charge accumulation region 53 for accumulating therein positive charges (holes).
The HAD structure is obtained in which the positive charge accumulation region 53 is formed in the interface of the silicon layer 51 in such a manner, whereby the photodiode PD is kept away from the interface, thereby making it possible to suppress the generation of the dark current with the interface states as the generation source.
In general, in forming the HAD structure, ions such as B ions or BF2 ions are implanted into the silicon layer 51 at an anneal temperature, thereby forming the p+-type semiconductor region becoming the positive charge accumulation region 53 in the neighborhood of the interface of the silicon layer 51.
Also, it is essential for an existing ion implantation process that for the purpose of realizing the proper diffusion and activation of the ions implanted, a high temperature is held for as long a time period as possible.
However, holding the high temperature for a long time period is not desirable from a viewpoint of sufficiently ensuring the characteristics or the like of the solid-state image pickup element.
FIG. 15A is a schematic cross sectional view explaining the case where an insulating layer having negative fixed charges is formed on a silicon layer having a photodiode formed therein. FIG. 15B is an energy diagram of the structure shown in FIG. 14A. As shown in FIGS. 15A and 15B, there is proposed a technique for forming an insulating layer 55 having negative fixed charges 54 on the silicon layer 51 having the photodiode PD formed therein. This technique, for example, is described in Japanese Patent Laid-Open No. 2008-306154 (referred to as Patent Document 2 hereinafter).
According to this technique, even when as shown in FIG. 15B, the ions are not implanted into the silicon layer 51 in a state in which a band is bent, the positive charge accumulation region 53 is formed in the neighborhood of the interface of the silicon layer 51, thereby making it possible to accumulate the positive charges (holes) in the positive charge accumulation region 53.
HfO2, ZrO2, Al2O3, TiO2, Ta2O5 or the like, for example, is given as a material for the insulating layer 55 having such negative fixed charges 54.